module LCD_On_FPGA(clk,
						reset_n,
						tft_wrx,
						tft_rdx,
						tft_csx,
						tft_dcx,
						tft_reset_n,
						tft_d_inout,
						tft_bl,
                  SEL,
   	            DIG,
						send_ready,
						addr_b,
						data_b,
						req_b,
						
);

	input clk,reset_n;
	output tft_wrx,tft_dcx,tft_rdx,tft_csx;
	output  tft_bl;
	inout[15:0]tft_d_inout;
	output  tft_reset_n;
   output 		   [7:0]       	SEL;
   output 		   [7:0]     	DIG;
	
	
	output					send_ready;
	input 	[19:0]		addr_b;
	input 	[15:0]		data_b;
	input 					req_b;

	

	/*********************************************************************/
						


	
	wire [15:0]write_d;
	wire [15:0]read_d;
	
	
	

	
	wire write_done_sig;
	wire read_done_sig;
	wire write_read_stop;
	wire[15:0]write_data;
	wire[15:0]read_data;
	wire[1:0]sig;//sig=2'b10传送的为地址命令 sig=2’b01传送为为数据
	wire wr_rd_sig;//wr_rd_sig=1 写 wr_rd_sig=0 读
	
	wire init_write_read_stop;
   wire init_done;
	wire [15:0]init_write_data;
	wire [1:0]init_sig;
	
	wire real_wr_rd_sig;
	wire [1:0]send_sig;
	wire [15:0]send_write_data;
	
	
	
		
	wire clk_r;
	wire[15:0]rd_addr;
	wire[15:0]picture_rd_data;
	wire[15:0]wr_addr;
	wire[15:0]picture_wr_data;
	wire picture_we;
	
	

	
	lcd_init init(  
				.clk(clk),
				.reset_n(reset_n),
				.init_done(init_done),
				.init_write_data(init_write_data),
				.init_sig(init_sig),
				.write_done_sig(write_done_sig),
				.init_write_read_stop(init_write_read_stop),
				.init_wr_rd_sig(init_wr_rd_sig),
				.tft_reset_n(tft_reset_n),
				);
	
	
	
	
	write_read U1(
				.clk(clk),
				.rstn(reset_n),
				.wrx(tft_wrx),
				.rdx(tft_rdx),
				.csx(tft_csx),
				.dcx(tft_dcx),
				.write_d(write_d),
				.read_d(read_d),
				.write_done_sig(write_done_sig),
				.read_done_sig(read_done_sig),
				.write_data(send_write_data),
            .read_data(read_data),				
				.sig(send_sig),
				.wr_rd_sig(real_wr_rd_sig),
				.write_read_stop(send_write_read_stop)
				);
	

    seg seg1(
            .clk(clk),
            .seg_data(read_data),
            .DIG(DIG),
            .SEL(SEL)
    );




 
	
	
draw_picture  draw_picture_u1 (
	.clk(clk), 
	.reset_n(reset_n),
	.picture_rd_data(data_b),
	.init_done(init_done),
	.clk_r(clk_r),
   .rd_addr(addr_b),
	.write_done_sig(write_done_sig),
	.sig(sig),
	.write_data(write_data),
	.wr_rd_sig(wr_rd_sig),
   .write_read_stop(write_read_stop),
	.ready(ready),
   .req_b(req_b)
);

	
	

	
	
	
	
	
	assign tft_bl = 1'b1;

	assign picture_we = 1'b0;
	assign real_wr_rd_sig = (~init_done)? init_wr_rd_sig : wr_rd_sig;
	assign tft_d_inout = wr_rd_sig ? write_d : 16'hzzzz;//wr_rd_sig控制三态门
	assign read_d =  tft_d_inout;
   
	assign send_sig = (~init_done)? init_sig : sig;
	assign send_write_data = (~init_done)? init_write_data : write_data;
	assign send_write_read_stop = (~init_done)? init_write_read_stop : write_read_stop;
	
   assign send_ready  =  init_done && ready; 

	



	/*****************************************************************/ 

						
						



endmodule
